武汉招聘

职位描述：
Description
We’re looking for Design For Test Engineer, responsibilities includes but not limited to:
1. Involve in top level test architecture definition and implementation.
2. Implement and verify DFT features for TAP controller and network, MBIST, repair, SCAN and test interfaces.
3. Collaborate among various functional groups for DFT tree built ups, e.g. clocking and power, logic place and synthesis.
4. Provide silicon bring-up support and debug.
5. In-house toolset, flow and methodology development.

Qualifications
1. Master degree or Bachelor with 2+ years of related experience, majoring in EE.
2. Knowledge of Verilog/VHDL experience with simulators and waveform debugging tools.
3. Familiar with various aspects of the frontend ASIC design flow including RTL design/verification and even physical design.
4. In-depth knowledge of DFT MBIST, Scan/ATPG, IEEE1500, etc.
5. Candidate with experience of ATPG will be considered with priority.
6. Good English communication both vocal and written.
7. Self-driven personality and team player. 举报 分享

As we are taking your candidature ahead we would like to highlight that INTEL as an organization believes & practices high standards of ethical behavior from every potential candidate. We at Intel are ethical in all aspects of business & we expect the same from our employees. As a prospective candidate, we trust that you will acknowledge & practice ethical behavior at all times.