上海招聘

Responsibilities:
- Independently handle key IC design tasks:
Block level Micro-architecture, RTL Design, Verification, Synthesis and timing closure.
Top level integration, including clock/reset implementation, synthesis and timing closure.
FPGA validation and Silicon bring-up.
- Participating in company's key engineering initiatives: Methodology improvement, new architecture study and proposal.
- Coordinating joint development with 3rd party:
IP selection/management and vendor coordination
Interface with 3rd party vendor for successful execution

Requirements:
Must have:
- BSEE Degree or equivalent
- 3-5 years of experience in hands-on IC design
- Familiarity with ASIC design methodology and SoC architecture.
- Familiarity with standard CAD tools including simulation, synthesis, formal verification tools.
- Self-motivated in solving problems
- Good communication skills and fluent in English.
- Good team player.

公司属于一家服务型公司。