上海招聘

Responsibility

Work with global med-end design team for large scale SOC chip design. Focus on Physical aware synthesis, test timing closure and full chip STA signoff for high performance SOC design.

    

You are expected to be owner of synthesis, timing closure in test mode, full chip timing signoff and provide technically leadership to the engineering team.

     Requirement:    

3+ years synthesis and STA experience. 1+ year DFT design experience

    

Timing signoff experience for 2+ Tapeout SOC Project Experience

    

Familiar with DCG, ICC2 or Genus. Experience with Fusion Compiler is plus.

    

Knowledge on DFT logic and structure.

    

Familiar with IP clock structure, like PCIE, Serdes, DDR.

    

7nm and beyond technology experience is big plus

    

Good at makefile, tcl and perl scripts

    

Work well with cross-functional teams

    

索喜科技（上海）有限公司是由日本富士通半导体事业部、日本松下半导体事业部以及日本国家开发银行共同注资成立于2014年12月，并于2015年3月成立开始运营。我们的品牌承诺 “for better quality of experience” 中充满了我们真诚的愿望。我们致力于进一步使产品质量走向高性能、高功能化，并向我们服务的客户以及未来世界的人们提供新的价值，为实现富裕社会贡献微薄之力。我们期待您的加入，同我们一起实现这美好的愿望。
更多信息，欢迎登陆我们的网站：************************/en/