上海招聘

Job Responsibilities:

l  Develop micro-architecture, write micro-architecture spec and other documents

l  Write RTL code, meet the function target and have good performance/power/area efficiency

l  Apply low power, DFT, DFD and other digital design techniques

l  Work with DV team to improve test plan and debug failed tests

l  Clean Lint, timing and other issues

l  Participate in silicon debugging

 

 

 

Job Requirements:

l  Master in electrics or computer engineering.

l  At least 3 years working experience in ASIC logic design

l  Expert of Verilog RTL design

l  Experience of large digital ASIC project

l  Familiar with front-end EDA tools and flows

l  Programming skill in SystemVerilog, C/C++, perl, Tcl/tk, Python, etc. is preferred

l  Familiar with Linux Environment

l  Good communication in both Chinese and English

l  Good team player and strong sense of responsibility

l  Strong problem solving skills

l  Have one or some of the following design experience: memory controller, graphics, cache, fabric, microprocessor.

  

  

上海天数智芯半导体有限公司（简称“天数智芯”）于2018年正式启动GPGPU大芯片设计，是中国一家GPGPU高端大芯片及超级算力提供商。
 
公司以“成为智能社会的赋能者”为使命，专注于云端服务器级的通用高性能计算大芯片，瞄准以云计算、人工智能、数字化转型为代表的数据驱动技术市场，解决核心算力瓶颈问题。重点打造自主可控、国际一流的通用、标准、高性能云端计算GPGPU大芯片，从芯片端解决算力问题；并推出面向5G应用需求的云端推理芯片，与进口主流GPGPU生态兼容，并提供国产化选项，意在将超级计算发展为水电煤一样的基础设施，以更可信、更高效、更经济的方式帮助各行业实现算力升级。