上海招聘

Job Description：

Logic synthesis: including std. cell mapping, timing, power, and area optimization. 

Physical implementation: including floorplan, power routing, placement, clock tree synthesis, routing, si fixing, drc fixing, timing closure, dfm, Flip Chip Routing ...etc. 

Physical verification: including low power check, timing analysis, timing eco, xtalk analysis, power analysis, ESD analysis, EM analysis, DRC check, LVS check, ANT check, ERC check ...etc. 

Tapeout: timing signoff, power signoff, design tapeout... etc. 

Qualification：

MS in ME/EE/CS, major in VLSI, logic design. Good GPA required

Hands-on experience in coding/circuit design or physical design is preferred

Detail oriented, self-motivated and team player. Good verbal and written communication skills

To qualify for the job, you should have some or all of the following technical background: 

a. Working knowledge of Digital Circuit, such as CMOS principle, combinational And sequential gate circuit, Layout and IC manufacture flow. 

b. Working knowledge of HDL, such as Verilog, VHDL and reading them easily.  

c. IC design methodologies using design automation EDA tools, ASIC design flow, and deep sub-micron technology. 

d. Familiarization with scripting programming (Tcl, Shell or Perl) is preferred. 

e.Known any of the EDA tools listed below: i. Synopsys: DC, ICC, PT, StartRC… ii. Cadence: RC, EDI, INNOVUS, TEMPUS, QRC… iii. Mentor: Calibre…

At Marvell, through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
You will be solving new technical challenges alongside leading industry professionals in an open, creative environment with plenty of opportunities for personal/professional growth.
By pursuing unexpected connections between regions, backgrounds, and perspectives, our cross-functional teams are continually pushing the boundaries of what’s possible for themselves and for technology.Join us.