上海招聘

Job Description：

Work together with top and design team to develop testplan and testcases for various blocks in our Preamp product
Maintain and help improve UVM based verification environment
Develop checker/driver and test cases to verify designs
Research on some advanced verification technology such as assertion based formal verification

Qualification：

Major in EE, CS or related
Familiar with Verilog and RTL design
Good problem solving and communication skills
Good written and spoken English. Be able to work together with global team
Familiar with System-Verilog and UVM verification methodology is a plus
Familiar with script languages (perl, tcl, sh etc.) is a plus

At Marvell, through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
You will be solving new technical challenges alongside leading industry professionals in an open, creative environment with plenty of opportunities for personal/professional growth.
By pursuing unexpected connections between regions, backgrounds, and perspectives, our cross-functional teams are continually pushing the boundaries of what’s possible for themselves and for technology.Join us.