ASIC Design Engineer - SOC
宽腾达通讯(无锡)有限公司上海分公司
- 公司规模:50-150人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-11-18
- 工作地点:上海
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位月薪:30-40万/年
- 职位类别:通信技术工程师
职位描述
Job Summary:
Design and develop WIFI SOC. The candidate must have strong knowledge of Processor integration, High Performance DDR3/4 Controller and Bus Fabric Integration. Ideal candidate must have strong background in various Interfaces like PCI Gen3/4, 10G Ethernet and XFI.
Responsibilities:
- Micro-architecture and RTL implementation of WIFI SOC modules from spec.
- Deliver RTL and detailed documentation to verification team, work with verification team on test plan and test coverage.
- Responsible for ASIC implementation of blocks which include lint, CDC, Synthesis, Timing constraints, formal verification, and STA.
- Interface with architecture, software, systems, and verification engineers during chip development stage and bring-up.
Qualifications:
- Minimum BS degree in EE Engineering and 6 years of experience. Preferably an MS in Electrical Engineering or computer Engineering.
- Experience in the micro-architecture and RTL coding of SOC , Processor Integration, Bus Fabric integration and DDR3/DDR4 controller.
- Experience in AXI and AHB interconnect fabrics, DMA, DDR controllers, high-speed peripherals (PCIe, SATA, USB), CPU/Cache, MMU/SMMU.
- Advanced knowledge of ASIC Design with keen understanding on Performance/Area/Power trade-off.
- Experience in ASIC implementation methodology steps like lint, CDC, Synthesis, formal verification, and STA and timing closure of DDR Controller.
- Proficient in Verilog and System Verilog for RTL design or verification.
- Experience of post silicon bring-up and debug is a plus.
- Excellent communication skills
职能类别:通信技术工程师
公司介绍
联系方式
- Email:hr-shanghai@quantenna.com
- 公司地址:地址:span中山南二路1089号徐汇苑大厦7楼