ASIC Design Methodology engneer
苏州兆芯半导体科技有限公司
- 公司规模：50-150人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-01-15
- 工作地点：苏州
- 招聘人数：若干
- 职位类别：集成电路IC设计/应用工程师
职位描述
Job Description
- Responsible for the development of ASIC design methodologies and flow automation for large and high speed chips using deep submicron processes.
- Responsible for the development t of automation flow for fundation IP test chip in advance process.
- Evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the frontend and backend design team.
Job Requirement
- 3 years of experience in large VLSI physical design implementation and automation and methodology.
- Strong experience in programming of one of the following area: C/C , Perl, Python.
- Experience with Floorplanning, Timing-Driven Placement, Routing and Optimization tools or equivalent EDA tools required.
- Knowledge of physical verification, static timing, power system design and analysis and signal integrity concepts and tools also required.
- Worked with advanced CMOS processes, with in-depth understanding of nanometer CMOS device/process technology, especially DFM/DFY issues.
- Basic familiarity with electro-migration/IR-Drop/Xtalk analysis, assembly concepts and physical synthesis would also be an advantage.
- ASIC frontend design experience is a plus
- Responsible for the development of ASIC design methodologies and flow automation for large and high speed chips using deep submicron processes.
- Responsible for the development t of automation flow for fundation IP test chip in advance process.
- Evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the frontend and backend design team.
Job Requirement
- 3 years of experience in large VLSI physical design implementation and automation and methodology.
- Strong experience in programming of one of the following area: C/C , Perl, Python.
- Experience with Floorplanning, Timing-Driven Placement, Routing and Optimization tools or equivalent EDA tools required.
- Knowledge of physical verification, static timing, power system design and analysis and signal integrity concepts and tools also required.
- Worked with advanced CMOS processes, with in-depth understanding of nanometer CMOS device/process technology, especially DFM/DFY issues.
- Basic familiarity with electro-migration/IR-Drop/Xtalk analysis, assembly concepts and physical synthesis would also be an advantage.
- ASIC frontend design experience is a plus
公司介绍
苏州兆芯半导体科技有限公司于2012年3月在苏州工业园区创意产业园成立，资金1800万元人民币，从事先进工艺基础IP库研发，为半导体设计公司提供全套基础IP库的解决方案。同时，为集成电路设计公司提供特种基础IP库的定制化及相关设计服务业务。公司将提供高度灵活的用人机制，有竞争力的薪酬待遇，为个人发展提供广阔的空间。我们期待您的加入，携手共进,与公司一起共同成长、共创双赢!