思科实习生项目 信号完整性工程师 IOT
思科系统(中国)研发有限公司
- 公司性质:外资(欧美)
- 公司行业:通信/电信/网络设备
职位信息
- 发布日期:2019-05-16
- 工作地点:上海
- 招聘人数:1人
- 工作经验:无工作经验
- 学历要求:硕士
- 职位类别:硬件工程师
职位描述
Responsibilities:
Involve the board level design with hardware related function team such as DE, ECAD, Diag, Power and so on to deliver high quality product.
Perform signal integrity simulations for high speed designs to reduce the potential risk
Lab measurement to verify the signal quality for the high-speed interfaces.
Analyze the failures found in testing and support the internal design team to find the root cause of the issues
工作职责:
参与板级的电路设计,并与硬件,布线,电源等相关小组的工程师协同工作
针对高速信号进行信号完整性相关的仿真设计来排除潜在的风险
通过实验测试来验证高速信号的信号质量
Requirements:
Knowledge with Electromagnetic Field Solvers, time and frequency domain simulation such as HFSS, CST, ADS, etc;
Experience correlating simulation results with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers;
Solid background on transmission line theory are necessary;
Fluent English speaking and writing;
Must be highly motivated and a quick learner;
工作要求:
了解电磁求解器,会使用HFSS, CST, ADS等软件进行时域和频域仿真;
熟练使用示波器,TDR,VNA和频谱分析器等,并与仿真结果进行一致性分析;
扎实的传输线理论的背景知识;
流利的英语口语和写作能力;
工作积极主动,学习能力强
Working time Requirements:
at least 3 months
at least 3 working days (from Monday to Friday) per week
9:00am-18:00pm per day
工作时间要求:
至少保证实习3个月
每周至少3个工作日(星期一至星期五)
每天9:00至18:00
Educational Background:
Second year master student in Electrical Engineering or related major.
学历:
研二,电子工程或者相关专业
Location:
Shanghai, Caohejing
工作地点:
上海,漕河泾
职能类别: 硬件工程师