上海招聘

职位描述：

CRDC (China R&D Center) ASIC team is developing ASICs for Cisco enterprise switching, routing, IOT and wireless products, with cutting edge methodology and technology. We developed first Cisco 2.5D chip with 100+ Million gates using Samsung 14nm technology. CRDC ASIC team has full-scale capability on architecture, design, DV, PD, DFT and bring up. We are now engaged in multiple projects, including next-Gen enterprise switching ASIC, next-Gen wireless/IOT ASIC, and enterprise routing FPGA.

CRDC ASIC团队主要开发思科企业网交换机，路由器以及无线网芯片。我们使用最先进的方法学，技术以及工艺。团队独立开发了思科第一颗2.5D、集成HBM的芯片，该芯片规模达到150M gates，使用三星14nm工艺。CRDC ASIC团队具有全流程完整的芯片开发技能，包括架构、设计、验证、后端、DFT以及上板调试。目前我们和全球团队共同开发多个项目，包括下一代企业网交换芯片，下一代无线/IOT芯片以及企业网路由器FPGA。

CRDC ASIC团队具有全球领先的开发技术，同时有团结轻松的工作氛围，我们以结果为导向，提供员工灵活、弹性、积极的工作环境

We are looking for a ASIC intern engineer to join our CAG Shanghai team for ASIC/FPGA development. In this role, you will have the opportunity to work with talents in the engineering team of CAG, participate CAG ASIC development.

我们正在寻找一名ASIC工程师实习生加入我们CAG上海团队进行ASIC/FPGA。在此职位上，您将有机会与CAG工程团队的人才合作，参与ASIC/FPGA的设计和验证。

Responsibilities:

1. Design and implementation of complex FPGAs and/or ASICs.

2. Participate in the architecture definition, implementation and verification phases.

3. Detailed design specification and test plan development.

4. Develop and implement block level RTL, perform synthesis and achieve timing closure.

工作职责：

1. 设计，验证大规模的网络芯片
2. 参与设计文档的编写，设计的实现并完成相应模块的验证
3. 开发测试平台，开发测试用例，调试测试结果
4. 开发RTL代码，综合以达到电路时序的要求

Requirements:

1. Knowledge on Verilog, SystemVerilog, C, C++

2. Skillful utilization of Verilog/System Verilog in complex logic design

3. Basic knowledge on Unix system and script tool is a plus

4. Good at both written and verbal in English.

5. Self-motivation, teamwork and strong communication skills are essential

技能要求：

1. 熟练掌握Verilog, SystemVerilog, C,C++
2. 熟练掌握用verilog/SV等语言进行逻辑设计
3. 了解并会应用Unix系统和脚本语言，提高工作效率
4. 较好的中英文写作能力和口语表达能力
5. 良好的团队协作能力

Working time Requirements:

· can work at least 3 months

· at least 3 working days (from Monday to Friday) per week

· 9:00am-18:00pm per day

工作时间要求：

· 至少保证实习3个月

· 每周最少3个工作日（星期一至星期五）

· 每天9:00至18:00

学历：

Educational Background：

Bachelor. ME,EE, CS or relevant Major preferred

硕士，微电子，电子，计算机相关专业

Location：

Shanghai, Caohejing

工作地点：

上海，漕河泾

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