上海招聘

职位描述：
Synthesis
Use DC (Design Compiler), ICC (IC Compiler) for chip synthesis with SDC either from RTL code or Gate level netlist. Cadence flow is welcome also.

Static Timing analysis and Formal verification
Perform timing analysis and timing optimization
Run formal verification after each ECO and timing optimization

Place & route, Physical verification

Knowledge about physical synthesis flow and floorplan; Familiar with place & route tools like encounter, ICC, Astro; Knowledge about process, DRC and LVS. Knowledge about DFM is better. Low power design knowledge is preferred.

DFT design: RTL coding; Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion; Memory BIST insertion; Logic BIST insertion; Test pattern generation and simulation; ATPG test vector generation and pattern simulation; Fault grading test vector generation; Memory BIST simulation; JTAG/NAND tree simulation; Test vector format conversion and provide all test related patterns to test and product engineers

 

任职要求：

§ Education/License:

BS is basic, MS is preferred

§ Working Experience:

0-3 years working experience on chip integration or related experiences in back end design

§ Professional Knowledge:

Strong Logic design and Semiconductor device physic background

Good English in both written and spoken 举报 分享

公 司 简 介
世芯电子（上海）有限公司是由美国硅谷工程师创办的外商独资企业，主要提供Fabless ASIC芯片设计技术服务。我们拥有世界一流芯片设计的团队，多次为海外公司成功地提供了基于45纳米µm、低功耗工艺的大型高端芯片的设计服务。
高尖端的科技是您通往事业之路的桥梁，理想的工作环境是您展示才华的舞台，现招聘致力于芯片设计的卓越人才加入我们：
About Us
Alchip Technologies Limited was founded in 2002 by semiconductor veterans from Silicon Valley and Japan with a business focus on turnkey fabless ASIC production for System-on-Chip (SoC) designs. The founding team has more than fifteen years experience on average in successfully developing high-complexity SoC products and has 100% first silicon success track record.

As chip complexity increases and process technology advances, physical design becomes the bottleneck of chip creation. According to Collett International Research, more than 65% of IC/ASIC designs required re-spins in 2003, seriously impacting product schedule and putting companies under tremendous time-to-market pressure. With excellent design expertise and proven SoC design methodology, Alchip enables customers achieve one-pass silicon success and therefore meet customers faster-time-to-market.

In addition to enabling customers faster-time-to-market, Alchip also helps customers reduce cost through design and product engineering. Facing today’s competitive markets, most semiconductor companies are under great cost pressure. Alchip endows customers cost advantage over competitors in the increasingly competitive markets.

In summary, customers will be able to focus on chip functionality and system design by outsourcing physical design and chip production to Alchip. Alchip’s leading-edge solutions ensure customers faster time to market and improved cost efficiency. It is a win-win for both sides.

Alchip currently has offices in Silicon Valley, Shin-Yokohama, Hsin-Chu, Taipei,Shanghai, Wuxi, Hefei,Guangzhou,Jinan.