ASIC Physical Design Engineer
宽腾达通讯(无锡)有限公司上海分公司
- 公司规模:50-150人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2017-04-15
- 工作地点:上海
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 语言要求:英语 良好
- 职位月薪:3-4万/月
- 职位类别:高级硬件工程师
职位描述
职位描述:
The roles:
Owning, and maintaining P & R scripts for block gate netlist to GDSII
P & R, extraction, Power IR, EM of block level and Physical verification
Work with front end engineer for timing closure activities
Requirements:
BSEE is required
3+ years of ASIC/SoC Physical Design; floor planning, power grid customization, P&R, CTS, DRC, LVS, etc...
Experience driving CTS to meet requirements
Experience with either one of P&R tools; Cadence EDI, or Synopsys IC Compiler
Proficiency using TCL, Perl and make scripting
举报
分享
The roles:
Owning, and maintaining P & R scripts for block gate netlist to GDSII
P & R, extraction, Power IR, EM of block level and Physical verification
Work with front end engineer for timing closure activities
Requirements:
BSEE is required
3+ years of ASIC/SoC Physical Design; floor planning, power grid customization, P&R, CTS, DRC, LVS, etc...
Experience driving CTS to meet requirements
Experience with either one of P&R tools; Cadence EDI, or Synopsys IC Compiler
Proficiency using TCL, Perl and make scripting
职能类别: 高级硬件工程师
关键字: Place and Route, P&R, timing, power
公司介绍
Quantenna (Nasdaq: QTNA) is a global leader and innovator of high performance Wi-Fi solutions. Founded in 2006, Quantenna has demonstrated its leadership in Wi-Fi technologies with many industry firsts into the market. Quantenna continues to innovate with the mission to perfect Wi-Fi by establishing benchmarks for speed, range, efficiency and reliability. Quantenna takes a multidimensional approach, from silicon, system to software, to assess Wi-Fi networks and provides total solutions for service providers worldwide. For more information, visit www.quantenna.com.
联系方式
- Email:hr-shanghai@quantenna.com
- 公司地址:地址:span中山南二路1089号徐汇苑大厦7楼