上海招聘

职位描述：
Job Summary:
PCS subsystem verification and SOC/external IP deployment support
Responsibility:
* Work with global PCS team to get a full deep insight on the design under test
* Subsystem level test bench setup/maintain, methodology deployment, verification component create/maintain
* Deploy SERDES container or provide technical consult support to SOCand external IP teams
* SERDES – SOC development plan alignment, i.e. create/maintain staging plan if needed
Education& Qualifications:
Candidate is preferred to be MSEE with minimum of 1 year, or BSEEwith minimum of 3-yearsexperience in digital ASIC/SOC design verification.
Experience:
1. Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) or multimedia/video is preferred.
2. Good knowledge of SystemVerilog and OVM is a plus.
3. Good knowledge of Verilog/C/C++/System C/SystemVerilog.
4. Verification insights into random techniques.
5. Verification of large scale ASICs.
6. Experience in power verification is an asset.
7. Verification of Virtualization Components is an asset.
8. Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
9. Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).

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As global leader in Engineering & R&D services, Altran offers its clients a new way to innovate by developing the products and services of tomorrow. Altran works on every link in the value chain of their project, from conception to industrialization. For over 30 years, the Group has provided its expertise to key players in the Aerospace, Auto, Defence, Energy, Life Sciences, Telecoms sectors etc… In 2017, the Altran group generated revenues of