合肥招聘

职位描述：

1.负责数字设计的后端实现，包括布局布线，timing sign-off，power sign-off；

2.和前端工程师紧密合作以优化时序/面积/功耗，并进行静态时序分析；

3.优化和验证流片的版图（包括寄生参数提取，ECO,DRC,LVS)；

4.电压降分析和优化，寄生参数的优化和芯片尺寸的优化；    

5.静态时序分析以及时序修正；  

6.形式验证。

    

薪酬福利待遇： 

1、 双休，五险一金、补充医疗保险（含配偶子女）、法定年休假+福利年假、节日福利等；   

2、一经录用，待遇从优。

    

任职资格：    

1.有后端布局布线并成功流片经验的优先；   

2.有Synopsys 或 Cadence 后端实现工具和流程经验的优先；   

3.熟悉一种或多种脚本语言(Perl,TCL或Shell)的优先；  

4.有前端和验证经验的优先。

    

Responsibilities: 

1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route, timing sign-off, power sign-off.    

2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.    

3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).    

4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.    

5. Static Timing analysis (Prime Time) and setup/hold fix.    

6. Formal Verification for equivalence checking (Formality).    

7. Generation of fill structures according to technology requirements.

    

Requirements:

1. Experience in backend design flow (APR) with proven SOC tape-out experience is a plus   

2. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.    

3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.   

4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.

芯思原微电子有限公司成立于2018年9月，坐落在安徽省合肥市高新技术产业园区。芯思原微电子有限公司由芯原微电子（上海）有限公司和美国新思科技等4家公司共同投资设立。
公司致力于先进高速及核心IP的研发，旨在为客户特别是中国本土客户提供性能优、风险低、易于整合验证及可靠性高的半导体集成电路知识产权核，助力客户开发及时满足市场需求的复杂芯片产品。