成都招聘

JOB DESCRIPTION:

1. Module-level RTL implementation base on design specification;
2. Module-level architecture definition and implementation base on DSP materials (C/C++ or Matlab)
3. Simulation/Verification at both module level and system level;
4. chip-level synthesis and timing closing;
5. Writing design spec and report;
6. FPGA/silicon debug on related modules.

JOB QUALIFICATIONS:

1. Bachelor degree or Master degree in ASIC Design Relevant;
2. >5 years of digital design experience;
3. Solid understanding of state-of-art tape-out flow and methodology from RTL to GDS; Strong hands-on experience in using widely-adopted EDA tools for netlist generation, formal check and timing fix; Broad knowledge base and good understanding of timing issues, P&R flow and challenges, DFT, low power design, signal integrity, test and packaging, handling of mixed signal, post-layout ECO, etc;
4. Familiar with C/C++ and Matlab and some script languages
5. Understanding the fundamentals of basic digital signal processing
6. Relevant experience with STB, especially with FEC and DDR is better.

澜至电子科技是全球一流的模拟与混合信号以及数字中央处理芯片供应商，为家庭娱乐市场提供高级安全智能及高集成度的全方位芯片解决方案。公司遵循ISO标准化流程和管理体系，凭借先进的研发平台及标准模块化的设计优势，通过专业高效的软件、测试和客户支持团队，为全球客户提供高性能、低功耗的芯片产品以及一流的技术支持和服务。