北京招聘模拟IC版图工程师

模拟IC版图工程师

Description:

Lead whole chip layout design, responsible for floorplan, schedule create and tape out action.
Responsible for the main block layout place and routing, DRC, LVS, ERC violation check. Responsible for top layout violation check.
Communication with design team, PM and foundry team.
Layout techniques to improve circuit performance, work with the team complete the project layout on time.
Work with design to define optimal layout solutions, based on design objectives.

Qualifications:

BS degree, 3+ years of analog IC layout experience, like bandgap voltage reference, devices matching and ESD/Latchup knowledge
Experience in high current, high voltage circuit layout, high accuracy Opamp
Experience in Cadence OA IC Layout tool set
Team-based, cross-functional organizational structure experience preferred
Strong communications skills; written, verbal, presentation and listening;
Good interpersonal skills to work in a team environment;
Good command of written and spoken English required;

仙童半导体技术（北京）有限公司诚聘