北京招聘

职位描述：
Job Responsibilities:
1) Set up reusable and high performance UVM environments for block and system level verification.
2) Develop random test sequence based on UVM platform and design function coverage for measure random test valuation.
3) Executing block or system simulation, give effective debug activate for platform or RTL bugs.
4) Have a good Cooperate with other teams with simulation support.
5) Develop scripts to make verification automatically.
6) Design and write verification plan, test features, test case plan and report documents.

Requirements:
1) 2+ years’ experience of digital verification
2) Proven track record for successful verification of IC products in the past, at least one successful tape-out experience.
3) Good background in Verilog/SystemVerilog and verification methodology, UVM/VMM is required.
4) Good knowledge of based on function coverage of random test method and assertion is a plus.
5) Knowledge of C is a plus.
6) Be familiar with ARM CPU based SOC design architecture.
7) Knowledge of block, sub system and system level verification concepts.
8) Knowledge and experience with Perl or python and Unix/Linux scripting strongly desired.

ams is a global leader in the design and manufacture of advanced sensor solutions. Leading manufacturers around the globe rely on ams’ sensing know-how for advanced systems design. For ams, “Sensing is Life”, and our passion is in creating the sensor solutions that make devices and technology smarter, safer, easier-to-use, and more eco-friendly. ams’ sensor solutions are at the heart of the products and technologies that define our world today – from smartphones and mobile devices to smart homes and buildings, industrial automation, medical technology and connected vehicles. Our products drive applications requiring small form factor, low power, highest sensitivity and multi-sensor integration. We offer sensors, interfaces and related software for consumer, communications, industrial, medical, and automotive markets.